15 Translation procedure

Chapter 15 Translation procedure The following flowcharts are an illustration of the sequence of events from the beginning of a translation to its final outcome. They represent an abstracted translation flow to summarize the information in the rest of this specification. The purpose is to indicate the end result of different types of transactions, in terms of transaction and translation success or error responses (including PCIe ATS errors and completion responses). Certain aspects are not intended to be depicted in detail, including but not limited to: • Atomic translation table update mechanism. • TLB conflict, configuration cache conflict (which might happen at an IMPLEMENTATION DEFINED point in the translation). • Speculative operations (which do not record errors or faults). • Attribute control. • Reporting of the events controlled by the SMMU_CR2.REC_CFG_ATS field. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 1108

Chapter 15. Translation procedure 15.1. Translation procedure charts 15.1 Translation procedure charts Outcome for Ordinary transac
on Outcome for ATS Transla
on Request Outcome for ATS Translated transac
on SMMUEN N TT? ATSCHK 1 Y 0 1 STE Fetch OK? Y EABT on STE fetch, cache lookup failure, or GPF. If OT: F_STE_FETCH, or F_CFG_CONFLICT N SMMU Bypass Terminate, abort Deny, UR Deny, CA Terminate, abort Terminate, abort Unpack/apply A
ributes if supported. Pass transacon Incoming ATS Translaon Request Incoming ordinary transacon Incoming ATS Translated transacon OT=TRUE TR=TRUE TT=TRUE Unsupported transacon? Terminate, abort Terminate, abort NOTE: F_UUT has IMPDEF priority and could be checked/ recorded later on – this placement is an example. Unsupported upstream transacon, F_UUT Shorthand, OT/TR/TT, for different types of incoming transacon SID range OK? N Y Bad StreamID. If OT: C_BAD_STREAMID N Invalid on bypass. TR: F_BAD_ATS_TREQ TT: F_TRANSL_FORBIDDEN Y 0 SEC_SID 1 ATS Translated not allowed on Secure StreamID. TT: F_TRANSL_FORBIDDEN Terminate, abort 0 Addr

OAS? N Terminate, abort Y Input address size is out of range (outside of OAS). TR? SEC_SID Y N 0 ATS Translaon Request not allowed on Secure StreamID. TR: F_BAD_ATS_TREQ 1 Deny, UR GBPA. Abort OT? Y N Apply GBPA a
ributes. 0 N 1 Terminate, abort (SEC_SID=10 || SEC_SID=1 && SIF=1) && InD=1 && PA space is Non-secure Terminate, abort Y Fetch & check STE A Is GPC enabled? Y To GPC N Is GPC enabled? Y To GPC Pass transacon N Figure 15.1: Translation Procedure Chart 1 ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 1109

Chapter 15. Translation procedure 15.1. Translation procedure charts Outcome for Ordinary transac
on Outcome for ATS Transla
on Request Outcome for ATS Translated transac
on STE valid, not ILLEGAL? STE.V=0 disables stream or STE.V=1 but contents ILLEGAL. If OT: C_BAD_STE N S1+S2 Bypass? TT? N N Fetch & check STE STE.EATS Y Y 10 (Split-stage ATS) Stream Bypass Deny, UR Terminate, abort Terminate, abort Terminate, abort Deny, CA 00 (ATS disabled) Terminate, abort STE.Config[2:0] must be 111 (both S1 & S2 translaon) for STE to be valid with EATS=10. For aributes, see chapter 13.6 PCIe and ATS aribute/ permissions handling. Pass transacon Y F_TRANSL_FORBIDDEN Perform STE.{INSTCFG, PRIVCFG, NSCFG} overrides as applicable. STE. Config 1xx Silently terminated, no event recorded. 000 TR: Illegal on bypass, F_BAD_ATS_TREQ TT: Illegal on bypass, F_TRANSL_FORBIDDEN Effecve STE.EATS=00 if STE.Config=100 TR? N Effecve STE.EATS Y F_BAD_ATS_TREQ 00 (ATS disabled) Deny, UR Other ATS TR and TT This is the only error recorded for ATS TRs. EATS=10 && ATSCHK=0 N Y (effecve EATS=00) Effecve value of STE.EATS=00 if Reserved value used To Stage 2 Check SSID Check for EATS=10 behaving as 00 if ATSCHK=0. TR or TT? Y OT: Apply STE override aributes SSID present? OT: No Stage 1 for substream, C_BAD_SUBSTREAMID Y N N Terminate, abort Terminate, abort Addr > OAS? N OT: Stage 1 F_ADDR_SIZE Y Terminate, abort OT & TR: Apply STE override aributes Terminate, abort Terminate, abort Deny, UR ((SEC_SID=01 && SIF=1) || SEC_SID=10) && InD=1 && PA space is Non-secure Y F_PERMISSION A Is GPC enabled? N Y Pass transacon N DPT check OK? F_TRANSL_FORBIDDEN N Y Terminate, abort Is GPC enabled? Y N 01 Perform STE.{INSTCFG, PRIVCFG, NSCFG} overrides as applicable. 01 (Full ATS enabled) 11 (Full ATS with DPT checks) To GPC To GPC 11 Here, ATSCHK=1 (as ATSCHK=0 TT exited the flowchart early, above). Therefore in this branch it checks against configuraon. Figure 15.2: Translation Procedure Chart 2 ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 1110

Chapter 15. Translation procedure 15.1. Translation procedure charts Outcome for Ordinary transac
on Outcome for ATS Transla
on Request Outcome for ATS Translated transac
on S1 translates? Y SSID present? N Substreams disabled. OT: C_BAD_SUBSTREAMID Y N n/a Terminate, abort Deny, CA Got VA SSID present? N No Stage 1 for substream. OT: C_BAD_SUBSTREAMID Y STE.CDMax > 0? N Y STE.CDMax > 0? N STE.S1DSS Y Non-substream traffic disabled. OT: F_STREAM_DISABLED 00 Other SSID > STE.CDMax Substream outside legal range. OT: C_BAD_SUBSTREAMID Y Other STE.S1DSS Substream 0 reserved. OT: F_STREAM_DISABLED Y N SSID=0 10 N Check Sub stream ID To Stage 2 Check SSID STE.S1DSS 10 Skip Stage 1 Addr > IAS? N S1 bypass address too large. OT: Stage 1 F_ADDR_SIZE Y Addr > IAS? S1 bypass address too large. OT: F_ADDR_SIZE Y 01 N Stage 1 + Stage 2 bypass dealt with above, so no-S1 implies S2 translates. CD table entry 0 used Terminate, abort Complete, R=W=0 B Figure 15.3: Translation Procedure Chart 3 ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 1111

Chapter 15. Translation procedure 15.1. Translation procedure charts Outcome for Ordinary transac
on Outcome for ATS Transla
on Request Outcome for ATS Translated transac
on CD fetch OK? EABT on fetch, cache lookup failure, or GPF. OT: F_CD_FETCH, or F_CFG_CONFLICT N S2 translates? N S2 translate OK? Y Y Transla
on-related fault at Stage 2 for CD- IPA. OT: F_TRANSLATION/F_ADDR_SIZE/ F_PERMISSION (/F_ACCESS, if STE.S2HA=0) (CLASS=CD, Stage=2) N 0 1 Fetch CD S2 translate for CD-IPA. HTTU: If STE.S2HA=1, set S2-TTD.AF=1 if not already set Y Non- transla
on read error? N Y STE.S2S S2 fault might be transient due to S2 paging. Or, if it’s a genuinely bad address, HV might respond by injecting F_CD_FETCH to guest Stall Terminate, abort Complete, R=W=0 Terminate, abort Deny, CA For Stage 1 + Stage 2 ATS (including Split-stage ATS, and with PRI at both levels), this case returns ‘R=W=0’ to elicit a PPR from the endpoint. The Hypervisor (HV) traps the PPR for VA and translates it to determine that the CD fetch faulted. The HV might make the page available and con
nue. However, if the guest used a genuinely bad CD IPA the nearest equivalent is an abort on CD read (from IPA). The guest can detect that ATS to a stream with a bad CD address seemed to succeed (R=W=0) instead of Deny, CA. In either case, device access is safely denied but the guest OS could detect a different error. Stage 2 TTD fetch EABT, TLB lookup failure, or GPF. OT: F_WALK_EABT (CLASS=CD, Stage=2), F_TLB_CONFLICT (Stage=2) CD valid? Y Invalid CD. OT: C_BAD_CD N Terminate, abort Deny, CA Walk Stage 1 n/a n/a B Figure 15.4: Translation Procedure Chart 4 ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 1112

Chapter 15. Translation procedure 15.1. Translation procedure charts Outcome for Ordinary transac
on Outcome for ATS Transla
on Request Outcome for ATS Translated transac
on Walk Stage 1 TT S2 translates? Read S1-TTD from PA Stage 1 TTD OK and not GPC fault? S2 walk for S1-TTD read IPA. HTTU: If STE.S2HA=1, update S2-TTD.AF=1 if not already set S2 translate OK? Y N N IPA translated to PA Last-level TTD? N Y Non- transla
on read error? N Stage 1 fault: OT: F_TRANSLATION, F_ADDR_SIZE, (F_ACCESS if last-level TTD && CD.HA=0), F_PERMISSION (affected by CD.HD=0) from S1- TTD of VA. (CLASS=IN, Stage=1) Or, F_PERMISSION due to SEC_SID=1 && InD=1 && SIF=1 && NS=1. Y Stage 2 fault: OT: F_TRANSLATION, F_ADDR_SIZE, F_PERMISSION, (F_ACCESS if STE.S2HA=0) from S2-TTD backing S1-TTD IPA. (CLASS=TT, Stage=2) 0 1 Non- transla
on read error? STE.S2S S1 HTTU required? S2 walk for S1-TTD write IPA. HTTU: If STE.S2HD=1 update S2-TTD.Dirty=1 if not already set Construct S1-TTD address (IPA/PA) Y S2 translate OK? Re-access Stage 2 TTD, but for write EABT on TTD read? N Stage 2 is R/O for S1-TTD. OT: F_PERMISSION from S2-TTD backing S1-TTD’s update IPA. (CLASS=TT, Stage=2) N 0 1 STE.S2S Race condi
on, no abort when it was read but now could EABT when write aempted Got IPA N 0 1 CD.S S2 translates? Update S1-TTD Y EABT on TTD write? N Y Stall Terminate, abort Complete, R=W=0 Terminate, abort Deny, CA Stall Terminate, abort Stall Terminate, abort Deny, CA Y N Atomic OT: F_WALK_EABT (CLASS=TT, Stage=1) N N Y Y S2 fault might be transient due to S2 paging. Terminate, abort Deny, CA CD.A 1 Terminate, RAZ/WI 0 CD.A=0 and CD.S=1 have no effect on a TR. ATS does not support RAZ/WI aborts. Y Terminate, abort Deny, CA OT: F_WALK_EABT (CLASS=TT, Stage=2) Terminate, abort Complete, R=W=0 Stage 2 TTD fetch EABT, TLB lookup failure, or GPF. OT: F_WALK_EABT (CLASS=TT, Stage=2), F_TLB_CONFLICT (Stage=2) Stage 1 TTD fetch EABT, TLB lookup failure, or GPF. OT: F_WALK_EABT (CLASS=TT, Stage=1), F_TLB_CONFLICT (Stage=1) NOTE: This flow depicts S2-TTD being updated with AF=1, then later Dirty=1 (e.g. fetch S1-TTD then later decide to update it – atomically). If S2 maps S1 read-only, could result in S2 having AF=1 yet later an S2 fault when Dirty update is aempted. n/a Walk Stage 1 n/a n/a Complete, R=W=0 Transla
on Fault?
N Input address out of range (considering StreamWorld, CD.TxSZ, CD.TBI), or effec
ve EPD Fault C Figure 15.5: Translation Procedure Chart 5 ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 1113

Chapter 15. Translation procedure 15.2. Notes on translation procedure charts Outcome for Ordinary transac
on Outcome for ATS Transla
on Request Outcome for ATS Translated transac
on Walk Stage 2 TT S2 trans? N Read S2-TTD from PA TTD OK and not GPC fault? Last TTD? Y Y S2 HTTU required? Got PA N Construct S2-TTD address (PA) Non- transla
on read error? Y Stage 2 fault: OT/TT: F_TRANSLATION, F_ADDR_SIZE, F_PERMISSION, (F_ACCESS if STE.S2HA=0), F_PERMISSION (affected by STE.S2HD=0) from S2-TTD of IPA (Stage=2, CLASS=IN) STE.S2S N 1 N Update S2-TTD EABT on S2- TTD Y N Pass transac
on (apply S1 ars) Complete, perms & PA from S1 table walk Terminate, abort Deny, CA Terminate, abort Stall Terminate, abort Complete, R=W=0 Terminate, abort 0 Pass transac
on (apply (S1+)S2 ars) Complete, perms & PA from (S1+)S2 table walk Pass transac
on (Combine in S2 ars) Terminate, abort Deny, CA Terminate, abort Atomic Atomic: May “load-exclusive, test/ manipulate, store-exclusive” in some systems or “read, test/manipulate, far CAS” or similar; if the TTD has changed in between, re-read TTD (i.e. GOTO Read S2-TTD) OT/TT: F_WALK_EABT (WALK=TTD, Stage=2) N Stage 2 TTD fetch EABT, TLB lookup failure, or GPF. OT/TT: F_WALK_EABT (CLASS=IN, Stage=2), F_TLB_CONFLICT (Stage=2) S2 fault might be transient due to S2 paging. To Stage 2 Skip Stage 1 EATS=01 && STE.Config[1]=0 Complete, PA=VA, U=0, R=W=1 N TR? Y N For regular EATS=01 ATS, Stage 1 has been skipped due to S1DSS=01 and Stage 2 does not translate. n/a Transla
on Fault?
Input address out of range (considering STE.S2T0SZ) Fault N TR && EATS=10? Y TR with EATS=10: Store IPA to return in final result, con
nue to Stage 2 for permissions (result’s permissions are combined S1+S2 permissions) Y TR && EATS=10? N Complete, perms from S1+S2; return IPA EATS=10? TR with EATS=10: Store Input address as IPA to return in result, con
nue to Stage 2 for permissions. N Y Terminate, abort (SEC_SID=10 || SEC_SID=1 && SIF=1) && InD=1 && PA space is Non-secure F_PERMISSION N Y n/a C Is GPC enabled? Y N Is GPC enabled? N N Is GPC enabled? N Y Y Is GPC enabled? N Pass transc
on (apply ars as appropriate) Complete (apply ars as appropriate) Pass transc
on (apply ars as appropriate) Y If S1DSS=01 causes Stage 1 to be skipped when EATS=10, the output address is the same as input (since EATS=10 means only Stage 1 is translated using ATS).
However, this carries on to Stage 2 to check permissions/aributes. See Chapter 15. To GPC Y To GPC Y To GPC GPC fault? N Y Terminate, abort Deny, CA Terminate, abort Figure 15.6: Translation Procedure Chart 6 15.2 Notes on translation procedure charts For every fault or termination that an ordinary transaction might experience, an ATS Translation Request has an equivalent defined response. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 1114

Chapter 15. Translation procedure 15.2. Notes on translation procedure charts Similarly, an ATS Translated transaction might experience a subset of the fault or termination reasons. Generally, situations that represent a configuration error result in a Completer Abort (CA) response to the endpoint, situations that represent an explicit prevention or disable of ATS service result in an Unsupported Request (UR) response, and Translation-related failures result in a successful Translation Completion having R == W == 0 (that is, no access for this address). See section 3.9.1.2 Responses to ATS Translation Requests. ARM IHI 0070 H.a Copyright © 2016-2026 Arm Limited or its affiliates. All rights reserved. Non-confidential 1115